1. Field of the Invention
The present invention relates to an information processing apparatus, an information processing method, and a computer program and, in particular, to an information processing apparatus, an information processing method, and a computer program appropriate for distributed processing performed by a plurality of processors.
2. Description of the Related Art
Distributed processing for distributing a process among a plurality of processors or computers for execution currently draws attention. In a first method, distributed processing is performed by a plurality of computers connected via a communication network. In a second method, distributed processing is performed among a plurality of processors arranged in a single computer. In a third method, the first method and the second method are combined.
An apparatus or a processor requesting the execution of distributed processing transmits data and a program, required to perform distributed process, to another apparatus or another processor which is going to perform distributed processing. Upon receiving the data and the program, the apparatus or the processor performs the requested process, and sends back processed data to the requesting computer or the requesting processor.
Upon receiving the data from the computer or the processor, the requesting computer or the requesting processor performs a predetermined process or records the received data.
Japanese Unexamined Patent Application Publications Nos. 2002-342165, 2002-351850, 2002-358289, 2002-366533, and 2002-366534 disclose high-speed computer architecture techniques that perform distributed processing using a uniform modular structure, a common computing module, and a uniform software cell.
With an ever-increasing clock speed and higher degree of integration implemented in information processing apparatuses, the use of a plurality of processors permits distributed processing to be performed without the need for a large-scale computer.
In the techniques stated in the above disclosure, a basic processing module is a processor element (PE). The PE includes a processor unit (PU), a direct-memory access controller (DMAC), and a plurality of additional processor units (APU), namely, a plurality of sub-processors for the main processor.
Known processor systems perform a variety of power control methods. Japanese Unexamined Patent Application Publication No. 9-34601 discloses a power control method in which each processor stops and resumes operation with a network and a system controller continuously kept running. Japanese Unexamined Patent Application Publication No. 2002-304232 discloses another power control method in which an operating frequency and a power supply voltage are controlled in response to loads. Japanese Unexamined Patent Application Publication No. 2001-526809 discloses yet another power control method in which a fault tolerance system blocks power to a central processing unit (CPU). Japanese Unexamined Patent Application Publication No. 2000-112559 discloses a power control system in which a multiprocessor system automatically detects no load state to control a clock frequency. Japanese Unexamined Patent Application Publication No. 2001-145174 discloses a power control method in which device cooperation is controlled in response to a change in environment and status.